The invention relates to an integrated circuit including a semiconductor device. In one embodiment the device includes a load current component, which has a multiplicity of trenches in a cell array, and a sensor component, which is integrated into the cell array of the load current component and has a sensor cell array, the area of which is smaller than the area of the cell array of the load current component by a specific factor, wherein measures are taken for an integration of the sensor component into the cell array of the load current component that is optimized with regard to matching.
In order to realize self-protecting MOS power switches, it is customary inter alia to integrate a current sensor on the power switch chip. The accompanying FIG. 7 illustrates a schematic circuit example of a MOS power switch equipped with a current sensor in high-side applications, the MOS transistors of said switch being n-DMOS transistors.
In a common embodiment, the current sensor is realized as a small DMOS sensor transistor Ts, which supplies a current proportional to the load current IL flowing through the load DMOS transistor if it is connected up to voltages identical to those of the load DMOS. Said DMOS sensor transistor Ts is e.g., a factor of 1000-10 000 smaller than the load DMOS, and a sensor current flows through it which is smaller than the load current IL through the load DMOS ideally by the geometrical ratio of the active areas of the two transistors, namely load DMOS and sensor transistor Ts. This ratio is called the ideal ratio KG of the currents hereinafter, to distinguish from the real ratio K of the currents.
If the integrated MOS power switch, as illustrated in FIG. 7, is realized using a common-drain technology, both transistors, that is to say load DMOS and sensor transistor Ts, have the same drain potential and the same gate potential. The source potential of the load DMOS is tapped off, as is illustrated e.g., in FIG. 7, and the source potential of the sensor transistor Ts is adjusted to the same potential. The real ratio K of the currents thus represents de facto the quotient of the on resistances of sensor transistor Ts and load DMOS.
In a practical embodiment, given a low load current, load DMOS and sensor transistor Ts are operated with a smaller gate-source voltage since, at high gate-source voltages, the voltage drop across the load DMOS would be small and the offset voltage of the differential amplifier U1 would correspondingly have a greater influence on the accuracy of the current measurement. Under these conditions, load DMOS and sensor transistor Ts are operated with a gate-source voltage near the threshold voltage and hence at an operating point at which the channel resistance predominates over the on resistance of the DMOS transistors. A difference in the threshold voltages of the two transistors, load DMOS and sensor transistor Ts, leads to large deviations of the real current ratio K from the ideal geometrical ratio Kg at this operating point.
Two operating modes are realized in practice:                operation with a high gate-source voltage even given small load currents. A good matching of the on resistance RON is important in this case. The accuracy of the current measurement is in this case limited by the offset of the differential amplifier connected downstream (cf. accompanying FIG. 7).        operation with a low gate-source voltage given small load currents. A good matching of the threshold voltage VES of the load DMOS and of the sensor transistor is important in this case since said matching limits the accuracy of the current measurement. The matching of the on resistance RON is once again important given large load currents (and a large gate-source voltage).        
In order to obtain a good accuracy of the current sensor under different operating conditions, load DMOS and sensor transistor Ts must have a good matching. Here matching should be understood to mean a coordination of the characteristic curves and identical threshold voltages of the two transistors. Furthermore, the sensor transistor is intended to be embedded into the active region of the load DMOS as well as possible in order to obtain a current density that is as homogeneous as possible in the vicinity of the sensor transistor Ts and thus comparable voltage drops e.g., in the substrate of the integrated MOS power switch.
A further embodiment for the embedding of the sensor transistor Ts is the ideally identical temperature of the two transistors. In the case of the conventional integrated MOS power switches, the distance between the load DMOS and the sensor transistor is relatively large in order to take account e.g., of the design rules (metal pitch, metal overlap) applicable in the customary technologies. In order to realize the embedding of the sensor transistor as well as possible, it may be necessary to minimize the distances between the sensor transistor and the load DMOS transistor.
For these and other reasons, there is a need for the present invention.